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this is information on a product in full production. for further information contact your local stmicroelectronics sales office. september 2013 doc id 16050 rev 5 1/20 20 STA2065 cartesio? family infotainment application pr ocessor with embedded gps data brief ? production data features arm1176 754/624/533 mhz host processor ? cache: 32 kb instruction, 32 kb data ? vector floating point unit high performance embedded gps subsystem ? parallel acquisition engines for 8 gps satellites or 4 galileo satellites ? 32 tracking channels for all satellites in view ? 5 correlators per channel for urban canyon robustness ? multibit signal processing hardware advanced power management ? separated power islands for ultra low power mode ? dynamic core frequency scaling ? 512-byte embedded sram for back-up system infrastructure ? lp ddr/ddr2 controller: 16/32-bit data 512 mb addressable (333 mhz ddr2, 200 mhz lpddr) ? one bank of 32 kb embedded sram ? 64-channel vector interrupt controller (vic) ? 2 dma controllers, 16 physical channels ? 32 dma request for each controller ? two external dma requests are supported display and graphics ? color lcd controller for stn,tft or hr- tft panels with 24-bit parallel rgb interface ? integrated touch screen controller and adc ? 3d advanced graphics acceleration ? video input port (vip) interface ? jpeg baseline profile decoder high throughput interfaces ? 2 ports usb 2.0 otg with integrated physical layers ? 3 sd/mmc up to 8 bit data, all bootable audio interfaces and features ? four multichannel serial ports (i2s/tdm) ? spdif input interface ? c3 hardware reed-solomon decoder ? sample rate converter standard interfaces ? four 16-bit input capture/output compare ? pulse width light modulator (pwl) ? four autobaud uart ? three i 2 c multimaster/slave interfaces ? two synchronous serial port (ssp, spi) ? smartcard interface ? 160 gpio over 5 32-bit ports two controllers area network (can) in automotive versions programmable voltage ios: 1.8 v, 2.5 v, 3.3 v v ddio_on : 1.8 10%v, v dd_on : v dd , 1.25 3%v tfbga 372+100 0.65 mm pitch package, packing in tray ambient temperature range: -40 / +85 c table 1. device summary order code grade cpu freq. can STA2065n2 consumer 533 mhz no STA2065p2 consumer 624 mhz no STA2065z2 consumer 754 mhz no STA2065a2 automotive 533 mhz 2x STA2065x2 automotive 624 mhz 2x STA2065y2 automotive 754 mhz 2x '!0'03 tfbga372+100 (16x16x1.2mm) www.st.com
contents STA2065 2/20 doc id 16050 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 system block diagram description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 mcu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 embedded memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2.1 embedded sram (esram) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 system functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3.1 system and reset controller (src) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3.2 pmu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3.3 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3.4 vectored interrupt controller (vic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3.5 gpios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3.6 real time clock (rtc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.7 real time timer (rtt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.8 always_on supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.9 enhanced function timer (eft) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3.10 watchdog timer (wdt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 memory interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4.1 flexible static memory controller (fsmc) . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4.2 sd/mmc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.3 ddr-sdram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.4 smart card interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 audio/video functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5.1 c3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5.2 sample rate converter (sarac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5.3 jpeg decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5.4 video input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5.5 smart graphics accelerator (sga) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5.6 color lcd controller (clcd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.1 usb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.2 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.3 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.4 msp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STA2065 contents doc id 16050 rev 5 3/20 2.6.5 ssp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.6 spdif . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6.7 ac97 controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6.8 can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7 specific functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7.1 gps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.7.2 touchscreen controller/adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7.3 multisupply io ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7.4 driving strength and slew rate programma bility . . . . . . . . . . . . . . . . . . . 12 3 system features introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 power region partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 frequency region partition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.3 frequency and power range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.4 power states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.5 system wakeup and power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 io groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
description STA2065 4/20 doc id 16050 rev 5 1 description STA2065 is a highly integrat ed soc application processor combining host capability with high performance embedded gps. STA2065 targets vehicle head units and mobile navigation (pnd), telematics, infotainment, advanced audio and connectivity systems. the STA2065 provides all the elements that are essential to build a cost effective solution. figure 1. application implementation example
STA2065 system block diagram description doc id 16050 rev 5 5/20 2 system block diagram description the STA2065 comprises the following functional blocks: 2.1 mcu arm1176-jzf advanced risc machine cpu up to 624 mhz (with v dd greater or equal to 1.20v and under process and temperature worst case conditions). 2.2 embedded memories 2.2.1 embedded sram (esram) the embedded sram is 8k x 32 (32 kbyte). 2.3 system functions 2.3.1 system and r eset controller (src) this provides a control interface for clock generation components external to the subsystem. it also controls system-wide and peripherals-specific energy management features. 2.3.2 pmu the power manager m odule controls the sleep to deep-sleep modes transition, controls the external voltage switches on the v dd and v ddio , monitors the external power supply (via two signals, vddok and batok), can force the emergency entry of the sdram in self-refresh, and controls the wake-up from deep-sleep mode. 2.3.3 dma direct memory access can be used with dma per ipherals. fifo fill/em pty requests from these peripherals can be serviced immediately by the dma controller without cpu interaction. peripheral-to-peripheral and memory-to-memory dma are also supported. STA2065 features two dma engines. each dma supports up to 8-channels and up to 32 requests. 2.3.4 vectored interrupt controller (vic) the vic allows the os interrupt handler to quickly dispatch interrupt service routines in response to peripheral interrupts. 2.3.5 gpios five gpio ports provide 160 programmable inputs or outputs that can be c ontrolled in two modes: software mode through an apb bus interface hardware mode through a hardware control interface
system block diagram description STA2065 6/20 doc id 16050 rev 5 2.3.6 real time clock (rtc) the rtc provides a one second resolution clock. this keeps time when the system is inactive and can be used to wake the system up when a programmed ?alarm? time is reached. it has a clock trimming feature to compensate the drift of the 32.768 khz crystal. 2.3.7 real time timer (rtt) the rtt has the possibility of being clocked off. this reduces the always_on domain consumption during deep sleep. by default the rtt has its clock enabled. 2.3.8 always_on supply the ?always_on? domain retains its two sepa rate supplies, one for the core logic (v dd_on ) and one for the ios (v ddio_on ). the v dd_on supply is equal to v dd during normal operation. 2.3.9 enhanced func tion timer (eft) STA2065 features 4 16-bit efts. each of the four eft timers has a 16-bit free-running counter with 7-bit prescaler, up to two input capture/output compare functions, a pulse counter function, and a pwm channel with selectable frequency. 2.3.10 watchdog timer (wdt) this os resource is used to trigger a system reset in the event of software failure. 2.4 memory interfaces 2.4.1 flexible static memory controller (fsmc) the flexible static memory controller (fsmc) supports, with two chip selects: rom static ram nor type flash memories, not multiplexed nor type flash memories, multiplexed it also supports, with two addit ional separate chip selects: nand type flash memories, slc small or large page nand type flash memories, mlc for nand type of memories, the fsmc has been enhanced to implement an error correction in hardware, based on the bose-chaudhuri-hocquenghem (bch) code, able to correct up to 8-bit over 512 bytes+syndrome. the bch code will calculate, in hardware, the syndrome only. the actual co rrection will be implemented through s/w in tervention.
STA2065 system block diagram description doc id 16050 rev 5 7/20 2.4.2 sd/mmc STA2065 features two sd/sdio/mmc interfaces up to 52 mhz / 8-bit. the main clock available to the peripherals is: pll2clk/13 (when pll2clk is 624 mhz and src_mmc52 = 0, 48 mhz will be generated) pll2clk/12 (when pll2clk is 624 mh z and src_mmc = 1, 52 mhz will be generated) pll2clk/9 (when pll2clk is 432 mhz, 48 mhz will be generated) the peripheral is compliant to the following standards: mmc 4.4 sd 2.0/part 1 - physical layer sd 2.0/part e1 - sdio specification 2.4.3 ddr-sdra m controller the sdram controller has been designed to support up to 1gbit over each of the two chip selects (or up to 2 gbit over a single chip select) of: lp ddr-sdram ddr2 the memory data bus will be 16 or 32-bit wide for lp d dr-sdram memories (under software control). this same configuration is also supported for ddr2 type of memories. 2.4.4 smart card interface STA2065 features a smart cart interface compliant to the standard iso7816-3. STA2065 supports 3.0 v or 1.8 v type of cards. 2.5 audio/video functions 2.5.1 c3 it is composed of cd-rom decoder block, responsible for performing sector de-scrambling and 3rd level of error correction embedded in the sector specific to cd-rom mode1 and xa form1, and data filter block supporting frame data filtering and different block layout organization possibilities. the c3 block can take its input data directly from spdif or from the memory space, and delivers back its output data to memory, supporting dma requests.
system block diagram description STA2065 8/20 doc id 16050 rev 5 2.5.2 sample rate converter (sarac) this block offers a fully digital stereo asynchronous sample rate conversion, using an automatic digital ratio locked loop. its main features are: up to 20-bit input and 22-bit output sample size dma optimized 16-bit stereo sample interface input sample rate from selectable msp or spdif interface (32 khz to 48 khz) output sample rate from selectable msp interface (44.1 khz to 48 khz) internally generated input sample rate (8 khz to 48 khz) for compressed audio decoding 2.5.3 jpeg decoder the jpeg decoder block performs baseline dct sequential decoding up to 16mpix/sec. jpeg compressed thumbnails are also supported. 2.5.4 video input STA2065 has a video input port. the vip allows to grab images from external devices, supporting parallel ccir-656 interface up to 80 mhz. this block can be used in camera mode with an imaging co -processor or a cvbs video decoder to store pixel information into system memory. it can be also used in raw mode to directly store raw data from an external sensor. 2.5.5 smart graphics accelerator (sga) the smart graphic accelerator (sga) provides an efficient 2d and 3d primitive drawing tool that breaks down the mips and power consumption concerns of pixel processing. 2.5.6 color lcd controller (clcd) this interface (18-bit parallel rg b) drives lcd panels. it supports single or dual-panel color and monochrome stn displays and color tft or hr-tft displays. the resolution can be 1, 2 or 4 bit-per-pixel (bpp) palletized for mono stn, 1, 2, 4 or 8 bpp palletized for color stn and tft, 16-bpp true-color non palletized for color stn and tft, 24-bpp packed or not packed true color non pallettized for color tft. it also offers frame modulation to deliver enhanced colors on 12, 16 or 18 bits (hr-) tft panels from up to 24-bpp format.
STA2065 system block diagram description doc id 16050 rev 5 9/20 2.6 communication interfaces 2.6.1 usb STA2065 embeds one usb2.0 otg high-speed interface named usb0 featuring: high-speed signalling ra te at 480 mbit/s support for full-speed (12 mbit/s) signaling bit rate support for session request protocol (srp) and host negotiation protocol (hnp) up to 7 bidirectional endpoints plus control endpoint 0 8192 bytes maximum fifo dimension dynamic fifo allocation usb0 is equipped with a built-in usb 2. 0 high-speed / otg phy, while usb1 is equipped with both an usb 2.0 full-speed phy and a standard ulpi interface able to connect to an external single date rate phy. with the goal of reducing the bom cost for the customer, the usb 2.0 phy also supports this additional muxing scheme: the usb d- wire is used as either the usb d- signal or uartn transmit data signal the usb d+ wire is used as either the u sb d+ signal or the uartn receive data signal 2.6.2 uart STA2065 features four autobaud uarts. one offers all modem control/status signals. they are enhanced versions of the industry-standard 16c550 uart. 2.6.3 i 2 c the i 2 c controller is an interface designed to support the physical and data link layer according to i 2 c standard revision 2.1 (january 2000). the i 2 c bus is a 2-wire serial bus that provides a low-cost interconnection between ics. STA2065 features three i 2 c interfaces. 2.6.4 msp the multichannel serial port (msp) is a synchronous receive and transmit serial interface. STA2065 features three msps. 2.6.5 ssp STA2065 features two ssps up to 24mbit/sec for synchronous serial communication with external peripherals. spi, microwire, t.i. and mono-directional protocols are supported with programmable word length up to 32 bits. 2.6.6 spdif this interface takes spdif as input and extracts data and other channel information encrypted in spdif frame format as per iec958 standards. data can be transferred to memory, using dma support, or directly to c3 decoder without cpu intervention. spdif block supports up to 2x data streams.
system block diagram description STA2065 10/20 doc id 16050 rev 5 2.6.7 ac97 controller ac97 audio controller enables soc to control external ac97 codecs using soc amba interconnect. it is implemented in a way to minimize audio data handling by soc processor with dedicated audio dma engine. ac97 audio controller supports ac97 revision 2.3 compliant audio codecs. external interface supports one external ac97 codec with 6 output (3 of them can be double rate audio) and 3 input channels. 2.6.8 can STA2065 features one can module that is comp liant with the can specification v2.0 part b (active). the bit rate can be programmed up to 1 mbaud. 2.7 specific functions 2.7.1 gps STA2065 integrates hpgps_g2, st?s proprietary gps ip, which is st?s 2nd generation high-sensitivity baseband. the baseband is fully compliant with gps and galileo l1/e1 signal specifications, and is optimized to ma ximize sensitivity for both acquisition and tracking in difficult environments. please refer to gps solution specifications and software release notes for more specific performance details. the baseband accepts a 3-bit signal at a 4mhz if from its companion rf chip, the sta5630. it down-converts this to baseband and feeds it to the acquisition engines (for up to 8 satellites simultaneously) and the trac king channels (for up to 32 satellites simultaneously). the highly parallel correlators in the acquisition engines identify each satellite signal in time and frequency domains, and the results are passed to the tracking channels. the tracking channels fine-tune the lock, then track continuously, providing orbit data and timing measurements to the arm cpus. the management of the hardware for these operations, and the myriad of complex conditions that arise, is performed in a comple te gps software library supplied by st. this library also takes the resultant measurement data and processes it to maintain satellite databases and calculate the user's position, velocity and time (pvt) solutions. the pvt solution, and other useful data, is made available to the user's application via an api in the st gps library. this runs on a roya lty-free real-time kernel (os20), with ports to industry-standard operating systems also available. in stand-alone mode, the outputs are generated in standard nmea message format. options are also available in the software library to support st self-trained assisted gps (st-agps), a complete and scalable solution for assisting gps start-up with autonomous ephemeris prediction when no network is available, and with simple download when a network is available followed by prediction for the following 7 days. the gps subsystem is based on an arm966 processor and is clocked by two clocks: mclk: arm966 cpu clock rfclk: 16f0 or 32f0, from rf chip mclk is derived from the pll2 clock with a divisor from 3 to 16, giving an arm966 operating frequency in the range from 208 to 39 mhz, in the case the pll2 is running at 624
STA2065 system block diagram description doc id 16050 rev 5 11/20 mhz. the same divisor will be from 2 to 16 when the pll2 is running at 432 mhz, giving an operating frequency in the range from 216 to 27 mhz. the gps baseband clock will be derived from t he mclk clock with a divider, internal to the subsytem, by 1, 2,3 or 4, under arm11 control. rfclk is the clock received from the rf front-end chip. 2.7.2 touchscreen controller/adc STA2065 embeds a 4-wire touch screen controller. the touch screen controller main characteristics are: active window clip movements tracking 12-bit sar adc resolution when used for touch screen (with averaging) measurement oversampling from 2 to 8 up to 128 coordinates fifo, with programmable fifo threshold adc minimum conversion time of 1 ? s capability to support 2 additio nal analog inputs for aux iliary functions like battery voltage monitoring and accessory control. the adc of the touch screen controller can be also used for the conversion of external analog signals. in this case the adc has a 10-bit resolution (its native resolution). 2.7.3 multisupply io ring STA2065 has multivoltage ios capable of supporting 1.8 v, 2.5 v or 3.3 v interfaces. the rings are defined as follows: a) all peripherals with exception of what belongs to other rings b) lcd c) dram d) fsmc e) mmc1 (gpio40-47, gpio76-82), can0 the default voltages app lied to each ring will be: a) 1.8v b) 1.8v c) 1.8v d) 1.8v e) 3.3v the ?always on? ring remains separated as in the current STA2065 and supplied by v ddio_on . note: for 1.8v and 3.3v io interfaces, pads are compensated across temperature and voltage variations but for 2.5v interface, pads are not compensated.
system block diagram description STA2065 12/20 doc id 16050 rev 5 2.7.4 driving strength and slew rate programmability the io driving strength is programmable for the following interfaces as follows: sd/mmc0 (4, 6, 8 ma) (default 8ma) sd/mmc1 (4, 6, 8 ma) (default 8ma) sd/mmc2 (4, 6, 8 ma) (default 8ma) lcd (4, 8 ma) (default 8ma) dram (weak 70w, strong 50w) (default strong, 50w) fsmc (4, 8 ma) (default 8ma) the slew rate is also controllable for the following interface as follows: sd/mmc0 (nominal, fast) (default nominal slew rate) sd/mmc1 (nominal, fast) (default nominal slew rate) sd/mmc2 (nominal, fast) (default nominal slew rate) lcd (nominal, fast) (default fast slew rate) fsmc (nominal, fast) (default fast slew rate) dram (200, 266, 333 mhz) (default 200 mhz) ulpi (nominal, fast) (default fast slew rate) msp0 (nominal, fast) (default nominal slew rate) msp1 (nominal, fast) (default nominal slew rate)
STA2065 system features introduction doc id 16050 rev 5 13/20 3 system features introduction in this chapter, an introduction to the main STA2065 system features is given. these will be explained in detail later in this document. 3.1 power region partition STA2065 is a device targeted to a wide range of applications, starting from handheld battery powered devices thanks to an optimized power management but also addressing in dash automotive power requirements thanks to its flexible multi-voltage io. three main power regions are identified: v dd_on : it is the core voltage that powers the rtc (real time clock), the pmu (power management unit), src (system clock and reset controller) and the backup ram of STA2065. v dd_on remains usually powered even wh en the device is in deep-sleep mode. for this reason, the static power consumption of this region stays below 20 ? a worst case. v dd : it is the core voltage that powers the overall chip (apart from the ios). this voltage is not applied in very low power state condition. when applied, the v dd_on and v dd are at the same voltage. a maximum of 10% variation between the two regions is required. v ddio : it is the power region dedicated to the ios. the overall ios are divided in seven groups and each of them can be powered at different, independent voltages. some groups may have specific constraints in terms of power voltage range in order to meet specific electrical characteristics compliant to some standards; some of these groups are, for example, in the ddr interface and the 1.1 embedded usb transceiver. there is also a group of ios called v ddio_on that identifies the ios that must be always powered (also in the lowest power consumption state of STA2065) in order to make the wake-up possible. the other five regions (called also v ddiox ) cannot be powered while in this state. for more in formation, please refer to chapter 3.6: io groups on page 17 3.2 frequency region partition STA2065 is designed so that there are two plls. pll1 generates clock frequencies for the arm core and the internal buses, while the pll2 generates clock frequencies for each peripheral kernel and also for each peripheral interface. this means that each peripheral receives the clock derived from the pll1 at its internal interface, then it works with the clock derived from the pll2. despite the use of two plls, a single system clock input or a single external crystal is needed (in addition to the rtc clock (or crystal)).
system features introduction STA2065 14/20 doc id 16050 rev 5 3.3 frequency and power range the core voltage range is 1.25 4% v while the io voltage ranges are 1.810% v, 2.5 10% v and 3.3 10% v ta bl e 2 shows some use cases of STA2065 in normal mode: the background of ta b l e 2 is the maximization of data throughput on the dram interface, matching the currently available dram speed grades: 133 mhz, 166 mhz and 200 mhz (lp ddr) and 333 mhz (ddr2). regardless of the memory speed grade it is possible to program the arm core, the internal bus and the ddr to run at different speeds than the ones mentioned in ta bl e 2 . the arm bus clock and the bus clock are derived from the same common source (vco of the pll1) but are asynchronous each other. the ddr frequency can be the same (synchronous) or derived with a different pre-scaling (1, 2, 3, 4, 5, 6, 8, 9 or 10) from the vco of pll1 or pll2 (asynchronous configuration). STA2065 embeds a complete gps subsystem where both gate logic and dedicated dsp work together. there are specific constraint s in this subsystem in terms of minimum frequency in order to guarantee the target gps specifications. in the lowest power consumption state possible, only v dd_on is powered and the target current drawn is 20 ? a. in this state, the clock is not running and the current leakage is mainly due to the backup memory. the 20 ? a current limit has to be considered with process best (leakage wo rst case condition), v dd_on 1.3v (1.25v plus 4% tolerance) and junction temperature 50 o c (considering, while in this state, the ambient temperature is equal to the junction temperature). table 2. frequency and power use cases v dd and v dd_on (v) core freq [mhz] bus freq [mhz] ddr freq [mhz] sync/async [s/a] 1.2 5(4%) 624 208 312 a, ddr2 1.2 5(4%) 624 156 156 s 1.2 5(4%) 624 124.8 124.8 s 1.2 5(4%) 533 177.67 177.67 s 1.2 5(4%) 533 133.25 133.25 s 1.2 5(4%) 533 177.67 312 a, ddr2 1.2 5(4%) 520 208 130 a 1.2 5(4%) 520 173.34 173.34 s 1.2 5(4%) 520 130 130 s 1.2 5(4%) 520 208 312 a, ddr2 1.2 5(4%) 494 197.6 197.6 s 1.2 5(4%) 494 164.67 164.67 s 1.2 5(4%) 494 123.5 123.5 s 1.2 5(4%) 494 208 329.34 a, ddr2
STA2065 system features introduction doc id 16050 rev 5 15/20 3.4 power states the following power states are defined: off : v dd_on and v dd are not applied (all data in the backup ram is lost): no data retention is kept in the sdram normal : each peripheral runs at its nominal speed with the possibility of turning off all the unused peripherals (peripheral kernel clock gated) slow : pll1 bypassed. arm and bus runs at cr ystal clock. pll2 runs at its nominal speed. pll1 can be optionally put in power down doze : it is like slow mode with the arm running either at 19 mhz or 32 khz standby : this power mode is achieved through software configuration of the normal mode. plls run at their nominal speed. arm1176 is in wfi (wait for interrupt) state and its clock is automatically gated off. deep-sleep : v dd powered off. v dd_on powered (rtc, few gpios, backup ram) and clocked at 32 khz making the wakeup possible. the context is put, optionally, in the external sdram if they are in self refresh mode. only the v dd and v ddio_on regions must be powered sleep : it is like the deep-sleep mode, with the difference that v dd and v ddio are also applied and the plls are off (optional for pll2) while in normal, slow and standby, v dd_on and v dd are the same (10% tolerance between them) and cannot be changed. also the power to the several io groups is kept unchanged. in order to change the v dd_on and v dd values, the system has to transit to either off, sleep, deep-sleep and then ba ck to the selected state. in order to keep the power consumption as low as possible, the target voltage mentioned in deep-sleep is considered at 1.0v. a dedicated fsm manages the power state transitions among normal, slow, doze and sleep. all other states mentioned above are sw variants of the ones managed by the fsm. ta bl e 3 shows the summary of the power states supported by STA2065. table 3. power mode states power state 32khz pll1 pll2 v dd_on v dd ios off off off off off off off normal on on on = v dd 1.2v to 1.3v (1.25v typ) 1.7 to 3.6v slow on off. bypassed by main oscillator off (sw can take it on) = v dd 1.2v to 1.3v (1.25v typ) 1.7 to 3.6v doze on off. bypassed by 32 khz off (sw can take it on) = v dd 1.2v to 1.3v (1.25v typ) 1.7 to 3.6v standby on on (clk gated) arm in wfi on (clk gated) = v dd 1.2v to 1.3v (1.25v typ) 1.7 to 3.6v
system features introduction STA2065 16/20 doc id 16050 rev 5 3.5 system wakeup and power down typically the system using STA2065 will never be powered off, even when the user switches the device off using the main power switch. the main power switch works in a way that puts the device in deep-sleep mode. in this state, the only bloc ks within STA2065 that are powered are the rtc, pmu, pwl, src and the backup ram; at system level, only the v dd_on is powered. the following wakeup methods are possible: the user presses a button on the unit that causes all of the main power supplies to start. after an appropriate delay, the processor's reset line is lifted and allows the code to start executing. the internal alarm feature triggers a dedicated signal that will cause all of the main supplies to start. after an appropriate delay, the processor's reset line is lifted and allows the code to start execution. considering the above mentioned wakeup system, while in deep-sleep, some dedicated io lines must be powered: por (input) poweren (output) vddok and batok (input) wake (input) 32khz xtal (sxtali and sxtalo) osc32kout (output) in order to keep the external dram in self refresh while in deep-s leep, cke of the dram must be kept low. since all the ios are not powered in deep-sleep, in order to make the self refresh working, an external pulldown resistor is needed. sleep on off off (sw can take it on) = v dd 1.2v to 1.3v (1.25v typ) 1.7 to 3.6v deep-sleep on off off 1.2 to 1.3v (1.25v typ) off refer section 3.5 table 3. power mode states (continued) power state 32khz pll1 pll2 v dd_on v dd ios
STA2065 system features introduction doc id 16050 rev 5 17/20 3.6 io groups v ddio is split into the following groups: v ddio_on (a) v ddiox (this is split into 5 types: v ddioa , v ddiob , v ddioc , v ddiod , v ddioe ) v usbphy (usb 2.0 hs phy transceiver) the io supply type and corresponding pads details are as follows: v ddio_on : power supply pins for the io buffers of the always on section. it supplies por, pwren, vddok, batok, wake, sxtali, sxtalo, osc32kout. v ddioa : power supply pins for the io buffers. it supplies most gpios, dedicated pads for jtag, mmc0 and gps and dedicated pads for test (scanen, tapsel). v ddiob : power supply pins for the io buffers. supplies to the clcd ios. v ddioc : power supply pins for the io buffers. supplies the synchronous dynamic memory controller (sdmc) ios. v ddiod : power supply pins for the io buffers. supplies the following ios: gpio9, gpio48:50, gpio64:67, gpio83:127 (fsmc). v ddioe : power supply pins for the io buffers. supplies the following ios: can, msp, gpios related to sd/mmc1 functionality. v usbphy : 3.3 v 10% usb pad power supply (it can be derated to 1.8 v in uart over usb mode and 1.8v signalling is desired). v ddtsc : 3.3 v touchscreen pad power supply a. vddio_on is always 1.8v.
package information STA2065 18/20 doc id 16050 rev 5 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 2. tfbga372+100 (16x16x1.2mm) mechanical data and package dimensions /54,).%!.$ -%#(!.)#!,$!4! $)- mm inch -). 490 -!8 -). 490 -!8 ! ! ! ! b $ $ % % e : ddd eee fff 4&"'! 4 hin profile & ine0itch " all ' rid ! rray "ody xxmmpitchmm " '!0'03
STA2065 revision history doc id 16050 rev 5 19/20 5 revision history table 4. document revision history date revision changes 23-jul-2009 1 initial release. 13-oct-2009 2 updated features list on page 1. 19-oct-2009 3 updated ?high throughput in terfaces? feature on cover page. 15-oct-2012 4 updated table 1: device summary on page 1 . 20-sep-2013 5 updated disclaimer.
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